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av:snes_sp_dif [2005/10/30 11:36] – Moved and fixed images. nfgav:snes_sp_dif [2006/04/03 15:39] – 172.161.20.252
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 Rather than draw up a schematic, I've made a table of the pins you need to connect.  The S-DSP column contains the pins you need to connect to if you have a two chip APU, and the S-APU column contains the pins you need to connect to if you have a single chip APU. Rather than draw up a schematic, I've made a table of the pins you need to connect.  The S-DSP column contains the pins you need to connect to if you have a two chip APU, and the S-APU column contains the pins you need to connect to if you have a single chip APU.
-[quote] +<code> 
-S-DSP S-APU CS8405A Pin +S-DSP S-APU CS8405A  Pin 
-33 3 +5VDC  1    COPY/C [CS bit 2] Copyright = 1 (allow copying) +33 3 +5VDC  1    COPY/C [CS bit 2] Copyright = 1 (allow copying) 
- 2 VL2+ + 2 VL2+ 
- 3 EMPH [CS bits 3-5] Emphasis = 0 (no emphasis) + 3 EMPH [CS bits 3-5] Emphasis = 0 (no emphasis) 
- 4 SFMT0 Data input is 16-bits right justified + 4 SFMT0 Data input is 16-bits right justified 
- 5 SFMT1 " " + 5 SFMT1 " " 
- 6 VD+ + 6 VD+ 
- 11 TCBLD TCBL is output + 11 TCBLD TCBL is output 
- 20 VL3+ + 20 VL3+ 
- 23 VL+ + 23 VL+ 
- 24 H/S Select hardware mode for controlling channel-status (CS) bit + 24 H/S Select hardware mode for controlling channel-status (CS) bit 
- 27 VL4++ 27 VL4+
    
-52 95 GND<sup>1</sup> 7 DGND4 +52 95 GND(1) 7 DGND4 
- 8 DGND3 + 8 DGND3 
- 10 APMS Set data input to slave mode (input is controlled by ISCLK) + 10 APMS Set data input to slave mode (input is controlled by ISCLK) 
- 16 CEN Select hardware mode A for setting channel status + 16 CEN Select hardware mode A for setting channel status 
- 17 V [Validity bit] Sub-frame contains valid sample data + 17 V [Validity bit] Sub-frame contains valid sample data 
- 18 U [User bit] Always 0 + 18 U [User bit] Always 0 
- 19 AUDIO<sup>2</sup>  [CS bit 1] Non-Audio = 0 (block contains audio data) + 19 AUDIO(2)  [CS bit 1] Non-Audio = 0 (block contains audio data) 
- 22 DGND + 22 DGND 
- 28 ORIG [CS bits 0 & 15] Pro = 0 (consumer format), L (Category Code MSB) = 0 (original recording)+ 28 ORIG [CS bits 0 & 15] Pro = 0 (consumer format), L (Category Code MSB) = 0 (original recording)
    
-47 16 RST  9 RST Reset +47 16 RST  9 RST Reset 
-43 94 32kHz  12 ILRCK Left/Right sample clock+43 94 32kHz  12 ILRCK Left/Right sample clock
 42 92 1.536MHz 13 ISCLK Sample bit clock 42 92 1.536MHz 13 ISCLK Sample bit clock
-44 93 DATA  14 SDIN Sample data input+44 93 DATA  14 SDIN Sample data input
 78 52  8.192MHz    21 OMCK Master clock 78 52  8.192MHz    21 OMCK Master clock
    
-Not connected  15 TCBL +Not connected  15 TCBL 
- 25 TXN+ 25 TXN
    
-Output  26 TXP S/PDIF output +Output  26 TXP S/PDIF output 
-[/quote]+</code>
 <sup>1</sup> Instead of grounding to the DSP, I soldered pin 28 of the CS8405A to the mainboard and tied all grounds there.  This doubled as a way to anchor the chip. <sup>1</sup> Instead of grounding to the DSP, I soldered pin 28 of the CS8405A to the mainboard and tied all grounds there.  This doubled as a way to anchor the chip.
  
av/snes_sp_dif.txt · Last modified: 2019/08/27 20:45 by 127.0.0.1