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--- schematics:megadrive1vdppinout [2005/11/10 04:14] – Grammer change aidan
+++ schematics:megadrive1vdppinout [2019/08/27 20:45] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
+==== VDP ====
+The Genesis/Megadrive contained a relatively powerful display processor (for the time), otherwise known as the VDP. This occupied position IC-8 on the circuit board, and is numbered 315-5313.
+^Pin^Name^Description^-^Pin^Name^Description^
+|1|SD0|Display RAM Data 0|-|65|CD10|68K Data 10|
+|2|SD1|Display RAM Data 1|-|66|CD11|68K Data 11|
+|3|SD1|Display RAM Data 2|-|67|CD12|68K Data 12|
+|4|SD1|Display RAM Data 3|-|68|CD13|68K Data 13|
+|5|SD1|Display RAM Data 4|-|69|CD14|68K Data 14|
+|6|SD1|Display RAM Data 5|-|70|CD15|68K Data 15|
+|7|SD1|Display RAM Data 6|-|71|CA0|68K Address 1|
+|8|SD1|Display RAM Data 7|-|72|CA1|68K Address 2|
+|9|-|Unknown|-|73|CA2|68K Address 3|
+|10|!SE 0|Display RAM !SOE|-|74|CA3|68K Address 4|
+|11|SC|Display RAM SC|-|75|CA4|68K Address 5|
+|12|!RAS|Display RAM !RAS|-|76|CA5|68K Address 6|
+|13|!CAS|Display RAM !CAS|-|77|CA6|68K Address 7|
+|14|-|Unknown|-|78|CA7|68K Address 8|
+|15|!WE|Display RAM !WE|-|79|CA8|68K Address 9|
+|16|!OE 1|Display RAM !DT/!OE|-|80|CA9|68K Address 10|
+|17|GND|Ground|-|81|CA10|68K Address 11|
+|18|-|Unknown|-|82|CA11|68K Address 12|
+|19|-|Unknown|-|83|CA12|68K Address 13|
+|20|-|Unknown|-|84|CA13|68K Address 14|
+|21|-|Unknown|-|85|CA14|68K Address 15|
+|22|-|Unknown|-|86|CA15|68K Address 16|
+|23|-|Unknown|-|87|CA16|68K Address 17|
+|24|-|Unknown|-|88|CA17|68K Address 18|
+|25|-|Unknown|-|89|CA18|68K Address 19|
+|26|AGC|Analog Ground|-|90|CA19|68K Address 20|
+|27|R|Red output|-|91|CA20|68K Address 21|
+|28|G|Green output|-|92|CA21|68K Address 22|
+|29|B|Blue output|-|93|CA22|68K Address 23|
+|30|AVC|Analog video supply voltage|-|94|AVS|Analog sound supply voltage|
+|31|AD0|Display RAM Address 0|-|95|PSG|PSG Sound output|
+|32|AVC|Display RAM Address 1|-|96|AGS|Analog sound ground|
+|33|AVC|Display RAM Address 2|-|97|GND|Ground|
+|34|AVC|Display RAM Address 3|-|98|!INT|Z80 Interrupt|
+|35|AVC|Display RAM Address 4|-|99|!BR|68K !BR|
+|36|AVC|Display RAM Address 5|-|100|!BGAK|68K !BGACK|
+|37|AVC|Display RAM Address 6|-|101|!BG|68K !BG|
+|38|AVC|Display RAM Address 7|-|102|!MRE0|Bus Arbiter !VDPN|
+|39|!YS|Video?|-|103|!BG|68K !BG|
+|40|SPA/B|Pulled up to VCC1|-|104|!IPL1|68K !IPL1 (Interrupt)|
+|41|!VSYNC|VSync to Bus Arbiter|-|105|!IPL2|68K !IPL2 (Interrupt)|
+|42|!C-SYNC|Composite Sync to encoder|-|106|!IREQ|Z80 IREQ|
+|43|!HSYNC|HSync to Bus Arbiter|-|107|!RD|Z80 !RD|
+|44|!HL|68K Halt?|-|108|!WR|Z80 !WR|
+|45|SEL0|!M3|-|109|!MI|Z80 !MI|
+|46|!PAL|NTSC flag input|-|110|!AS|68K !AS|
+|47|!RESET|!SRES|-|111|!UDS|68K !UDS|
+|48|SELI|Pulled down to GND|-|112|!LDS|68K !LDS|
+|49|!CLKI|68K Clock out|-|113|R/!W|68K Read/!Write|
+|50|SBCR|SBCR (X in)|-|114|!DTAK|68K !DTACK|
+|51|CLK0|Z80 Clock out|-|115|!UWR|68K memory !UWR|
+|52|MCLK|Master Clock in|-|116|!LWR|68K memory !LWR|
+|53|EDCK|HS_CLK in|-|117|!OE0|68K memory !OE0|
+|54|VDD|VCC1|-|118|!CAS0|68K memory !CAS0|
+|55|CD0|68K Data 0|-|119|!RAS0|68K memory !RAS0|
+|56|CD1|68K Data 1|-|120|-|Unknown|
+|57|CD2|68K Data 2|-|121|-|Unknown|
+|58|CD3|68K Data 3|-|122|-|Unknown|
+|59|CD4|68K Data 4|-|123|-|Unknown|
+|60|CD5|68K Data 5|-|124|-|Unknown|
+|61|CD6|68K Data 6|-|125|-|Unknown|
+|62|CD7|68K Data 7|-|126|-|Unknown|
+|63|CD8|68K Data 8|-|127|-|Unknown|
+|64|CD9|68K Data 9|-|128|VDD|VCC1|
+Note:\\
+Oddities with the way that memory is connected to the VDP means that the local V-RAM chips are split across a dedicated data bus and a shared data/address bus. I'm not sure why this is!