Differences

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--- schematics:megadrivecart [2005/11/09 11:41] – aidanii
+++ schematics:megadrivecart [2019/08/27 20:45] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
+==== Genesis/Megadrive cartridge pinout ====
+The following table describes the pinout for the Genesis/Megadrive cartridge port. With the console facing you, row A is the rearmost row, and row B is the frontmost row. Numbering starts from left to right.\\
+\\
+^pin^Name^Description^-^pin^Name^Description^
+|A01|GND|Ground|-|B01|SL1|Sound input left|
+|A02|5v|VCC1|-|B02|!HRST|Hard reset|
+|A03|A08|Address 08|-|B03|SR1|Sound input right|
+|A04|A11|Address 11|-|B04|A09|Address 09|
+|A05|A07|Address 07|-|B05|A10|Address 10|
+|A06|A12|Address 12|-|B06|A18|Address 18|
+|A07|A06|Address 06|-|B07|A19|Address 19|
+|A08|A13|Address 13|-|B08|A20|Address 20|
+|A09|A05|Address 05|-|B09|A21|Address 21|
+|A10|A14|Address 14|-|B10|A22|Address 22|
+|A11|A04|Address 04|-|B11|A23|Address 23|
+|A12|A15|Address 15|-|B12|!YS|Video|
+|A13|A03|Address 03|-|B13|!VSync|Vsync|
+|A14|A16|Address 16|-|B14|!HSync|HSync|
+|A15|A02|Address 02|-|B15|HS_CLK|VCLK|
+|A16|A17|Address 17|-|B16|!C_OE|!AS|
+|A17|A01|Address 01|-|B17|!C_CE|!CE0|
+|A18|GND|Ground|-|B18|!AS|Address strobe|
+|A19|D07|Data 7|-|B19|CLK|68000 clock|
+|A20|D00|Data 0|-|B20|!DTACK|Data ack|
+|A21|D08|Data 8|-|B21|!CAS_2|!CAS_2|
+|A22|D06|Data 6|-|B22|D15|Data 15|
+|A23|D01|Data 1|-|B23|D14|Data 14|
+|A24|D09|Data 9|-|B24|D13|Data 13|
+|A25|D05|Data 5|-|B25|D12|Data 12|
+|A26|D02|Data 2|-|B26|!LO_MEM|!ASEL|
+|A27|D10|Data 10|-|B27|!RST |68K reset|
+|A28|D04|Data 4|-|B28|!LDS|Lower data strobe|
+|A29|D03|Data 3|-|B29|!UDSW|Upper data strobe|
+|A30|D11|Data 11|-|B30|!SRST|Soft reset|
+|A31|5v|VCC1|-|B31|!TIME|Unknown|
+|A32|GND|Ground|-|B32|!C_DTCT|Cart detect - disables onboard ROM(s)|
+Notes:\\
+Address and Data busses are from the 68000 perspective.\\
+VCC1 supplies power to the 68000 and the YM2612 and possibly some other minor parts.\\
+VCC2 supplies power to the Z80, memory and custom chips. They are generated by two seperate voltage regulators. \\
+CLK and HS_CLK are not synchronous, just in case you want to do anything funky (like I did).\\