x68000:exp_port
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+ | All information on this page was taken from: http:// | ||
+ | |||
+ | ===== X68000 I/O Expansion Slot ===== | ||
+ | | | **Side A**| | | |**Side B** | | | ||
+ | | | GND|**1**| |**51**|GND | ||
+ | | 20MHz Clock| | ||
+ | | | GND|**3**| |**53**|10M | ||
+ | | Data Bus| DB00|**4**| |**54**|E | ||
+ | | Data Bus| DB01|**5**| |**55**|AB00 | ||
+ | | Data Bus| DB02|**6**| |**56**|AB01 | ||
+ | | Data Bus| DB03|**7**| |**57**|AB02 | ||
+ | | Data Bus| DB04|**8**| |**58**|AB03 | ||
+ | | Data Bus| DB05|**9**| |**59**|AB04 | ||
+ | | Data Bus| DB06|**10**| |**60**|AB05 | ||
+ | | | GND|**11**| |**61**|GND | ||
+ | | Data Bus| DB07|**12**| |**62**|AB06 | ||
+ | | Data Bus| DB08|**13**| |**63**|AB07 | ||
+ | | Data Bus| DB09|**14**| |**64**|AB08 | ||
+ | | Data Bus| DB10|**15**| |**65**|AB09 | ||
+ | | Data Bus| DB11|**16**| |**66**|AB10 | ||
+ | | Data Bus| DB12|**17**| |**67**|AB11 | ||
+ | | Data Bus| DB13|**18**| |**68**|AB12 | ||
+ | | Data Bus| DB14|**19**| |**69**|AB13 | ||
+ | | Data Bus| DB15|**20**| |**70**|AB14 | ||
+ | | | GND|**21**| |**71**|GND | ||
+ | | +12V| +12V|**22**| |**72**|AB15 | ||
+ | | +12V| +12V|**23**| |**73**|AB16 | ||
+ | | CPU Function Code| FC0|**24**| |**74**|AB17 | ||
+ | | CPU Function Code| FC1|**25**| |**75**|AB18 | ||
+ | | CPU Function Code| FC2|**26**| |**76**|AB19 | ||
+ | | Address Bus Confirm| | ||
+ | | Lower Data Strobe| | ||
+ | | Upper Data Strobe| | ||
+ | | Transfer Direction| | ||
+ | | | GND|**31**| |**81**|GND | ||
+ | | -12V| -12V|**32**| |**82**|HSYNC | ||
+ | | -12V| -12V|**33**| |**83**|VSYNC | ||
+ | | Address Bus Valid| | ||
+ | | Peripheral is addressed around 68000 family (??? | ||
+ | | Data Transfer Acknowledge| | ||
+ | | External Reset| | ||
+ | | In: CPU Halt, Out: System Stop| HALT|**38**| |**88**|EXPCL | ||
+ | | External Bus Error| | ||
+ | | External Power On| EXPW.ON|**40**| |**90**|EXNMI | ||
+ | | | GND|**41**| |**91**|GND | ||
+ | | +5V| Vcc2|**42**| |**92**|IRQ2-n | ||
+ | | +5V| Vcc2|**43**| |**93**|IRQ4-n | ||
+ | | Memory Row/Column Switch Signal| | ||
+ | | Memory CAS Signal (Read)| | ||
+ | | Memory CAS Signal (Write Lower)| | ||
+ | | Memory CAS Signal (Write Upper)| | ||
+ | | Main Memory Refresh Cycle| | ||
+ | | +5V| Vcc1|**49**| |**99**|Vcc1 | ||
+ | | +5V| Vcc1|**50**| |**100**|Vcc1 | ||
x68000/exp_port.txt · Last modified: 2019/08/27 20:45 by 127.0.0.1