Differences

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--- x68000:dmac [2017/09/11 09:53] – added DCR register neko68k
+++ x68000:dmac [2017/09/11 10:17] – added SCR register neko68k
@@ Line 19: / Line 19: @@
 |+0x02|1.w| |---|
 |+0x04|1.b|R/W|[[dmac#dcr|DCR]] - Device Control Register|
-|+0x05|1.b|R/W|OCR - Operation Control Register|
+|+0x05|1.b|R/W|[[dmac#ocr|OCR]] - Operation Control Register|
-|+0x06|1.b|R/W|SCR - Sequence Control Register|
+|+0x06|1.b|R/W|[[dmac#scr|SCR]] - Sequence Control Register|
 |+0x07|1.b|R/W|CCR - Channel Control Register|
 |+0x08|1.w| |---|
@@ Line 100: / Line 100: @@
 |  2  |0|
 |  1~0  |PCL - Peripheral control line \\ %00: Status input \\ %01: Status input with interrupt \\ %10: 1/8 pulse start \\ %11: ABORT input (forced termination)|
+---
+OCR<BOOKMARK:ocr> - Operation Control Register (+0x05)
+^  7  ^  6  ^  5  ^  4  ^  3  ^  2  ^  1  ^  0  ^
+|  DIR  |  BIT  |  SIZE  ||  CHAIN  ||  REQG  ||
+^Bits^Description^
+|  7  |DIR - Direction \\ %0: Memory->Device (MAR->DAR) \\ %1: Device->Memory (DAR->MAR)|
+|  8  |BTD - Multiple block transfer DONE \\ %0: Normal operation \\ %1: If there is a DONE signal, forcibly transfer the next block.|
+|  5~4  |SIZE - Operand size \\ %00: Byte (8-bits) \\ %01: Word (16-bits) \\ %10: Longword (32-bits) \\ %11: No pack size. Port size 8-bits. Byte (8-bits) transfer|
+|  3~2  |CHAIN - Chaining mode \\ %00: No chain \\ %01: Unused \\ $10: Array chaining \\ %11: Link array chaining|
+|  1~0  |REQG - Request generation method \\ %00: Speed limit auto request \\ %01: Max speed auto request \\ %10: External transfer request (by REQ line) \\ %11: Auto request first transfer, external request from second transfer onward.|
+Note: Channel #0, #1, and #3 should be used with external transfer request.
+---
+SCR<BOOKMARK:scr> - Sequence Control Register (+0x06)
+^  7  ^  6  ^  5  ^  4  ^  3  ^  2  ^  1  ^  0  ^
+|0||||MAC||DAC||
+^Bits^Description^
+|  7~4  |0|
+|  3~2  |MAC - Memory address count \\ %00: Do not change memory address register \\ %01: Increment memory address register each time transfer is done \\ %10: Decrement memory address register each time transfer is done \\ %11: Unused|
+|  1~0  |DAC - Device address count \\ %00: Do not change device address register \\ %01: Increment device address register each time transfer is done \\ %10: Decrement device address register each time transfer is done \\ %11: Unused|