x68000:dmac
Differences
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x68000:dmac [2017/09/11 10:09] – added OCR register neko68k | x68000:dmac [2017/09/11 10:49] – added CPR, DFC, BFC, and GCR registers neko68k | ||
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Line 20: | Line 20: | ||
|+0x04|1.b|R/ | |+0x04|1.b|R/ | ||
|+0x05|1.b|R/ | |+0x05|1.b|R/ | ||
- | |+0x06|1.b|R/ | + | |+0x06|1.b|R/ |
- | |+0x07|1.b|R/ | + | |+0x07|1.b|R/ |
|+0x08|1.w| |---| | |+0x08|1.w| |---| | ||
- | |+0x0A|1.w|R/ | + | |+0x0A|1.w|R/ |
- | |+0x0C|1.l|R/ | + | |+0x0C|1.l|R/ |
|+0x10|1.l| |---| | |+0x10|1.l| |---| | ||
- | |+0x14|1.l|R/ | + | |+0x14|1.l|R/ |
|+0x18|1.w| |---| | |+0x18|1.w| |---| | ||
- | |+0x1A|1.w|R/ | + | |+0x1A|1.w|R/ |
- | |+0x1C|1.l|R/ | + | |+0x1C|1.l|R/ |
|+0x20|1.l| |---| | |+0x20|1.l| |---| | ||
|+0x24|1.b| |---| | |+0x24|1.b| |---| | ||
- | |+0x25|1.b|R/ | + | |+0x25|1.b|R/ |
|+0x26|1.b| |---| | |+0x26|1.b| |---| | ||
- | |+0x27|1.b|R/ | + | |+0x27|1.b|R/ |
|+0x28|1.b| |---| | |+0x28|1.b| |---| | ||
- | |+0x29|1.b|R/ | + | |+0x29|1.b|R/ |
|+0x2A|1.w| |---| | |+0x2A|1.w| |---| | ||
|+0x2C|1.b| |---| | |+0x2C|1.b| |---| | ||
- | |+0x2D|1.b|R/ | + | |+0x2D|1.b|R/ |
|+0x2E|1.w| |---| | |+0x2E|1.w| |---| | ||
|+0x30|1.b| |---| | |+0x30|1.b| |---| | ||
- | |+0x31|1.b|R/ | + | |+0x31|1.b|R/ |
|+0x32|3.w| |---| | |+0x32|3.w| |---| | ||
|+0x38|1.b| |---| | |+0x38|1.b| |---| | ||
- | |+0x39|1.b|R/ | + | |+0x39|1.b|R/ |
|+0x3A|1.l| |---| | |+0x3A|1.l| |---| | ||
|+0x3E|1.b| |---| | |+0x3E|1.b| |---| | ||
- | |+0x3F|1.b|R/ | + | |+0x3F|1.b|R/ |
===== Register Descriptions ===== | ===== Register Descriptions ===== | ||
Line 111: | Line 111: | ||
| 7 |DIR - Direction \\ %0: Memory-> | | 7 |DIR - Direction \\ %0: Memory-> | ||
| 8 |BTD - Multiple block transfer DONE \\ %0: Normal operation \\ %1: If there is a DONE signal, forcibly transfer the next block.| | | 8 |BTD - Multiple block transfer DONE \\ %0: Normal operation \\ %1: If there is a DONE signal, forcibly transfer the next block.| | ||
- | | 5~4 |SIZE - Operand size \\ %00: Byte (8-bits) \\ %01: Word (16-bits) \\ %10: Longword (32-bits) \\ %11: No pack size. Port size 8-bits. Byte (8-bits) transfer)| | + | | 5~4 |SIZE - Operand size \\ %00: Byte (8-bits) \\ %01: Word (16-bits) \\ %10: Longword (32-bits) \\ %11: No pack size. Port size 8-bits. Byte (8-bits) transfer| |
| 3~2 |CHAIN - Chaining mode \\ %00: No chain \\ %01: Unused \\ $10: Array chaining \\ %11: Link array chaining| | | 3~2 |CHAIN - Chaining mode \\ %00: No chain \\ %01: Unused \\ $10: Array chaining \\ %11: Link array chaining| | ||
- | | 1~0 |REQG - Request generation method \\ %00: Speed limit auto request \\ %01: Max speed auto request \\ %10: External transfer request (by REQ line) \\ %11: Auto request first transfer, external request from second transfer | + | | 1~0 |REQG - Request generation method \\ %00: Speed limit auto request \\ %01: Max speed auto request \\ %10: External transfer request (by REQ line) \\ %11: Auto request first transfer, external request from second transfer |
Note: Channel #0, #1, and #3 should be used with external transfer request. | Note: Channel #0, #1, and #3 should be used with external transfer request. | ||
+ | |||
+ | --- | ||
+ | |||
+ | SCR< | ||
+ | |||
+ | ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | ||
+ | |0||||MAC||DAC|| | ||
+ | |||
+ | ^Bits^Description^ | ||
+ | | 7~4 |0| | ||
+ | | 3~2 |MAC - Memory address count \\ %00: Do not change memory address register \\ %01: Increment memory address register each time transfer is done \\ %10: Decrement memory address register each time transfer is done \\ %11: Unused| | ||
+ | | 1~0 |DAC - Device address count \\ %00: Do not change device address register \\ %01: Increment device address register each time transfer is done \\ %10: Decrement device address register each time transfer is done \\ %11: Unused| | ||
+ | |||
+ | --- | ||
+ | |||
+ | CCR< | ||
+ | |||
+ | ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | ||
+ | | STR | CNT | HLT | SAB | INT | 0 ||| | ||
+ | |||
+ | ^Bits^Description^ | ||
+ | | 7 |STR - Start operation \\ %1: Start operation| | ||
+ | | 6 |CNT - Continue operation \\ %0: No continuous operation \\ %1: Continuous operation| | ||
+ | | 5 |HLT - Halt operation \\ %1: Pause channel| | ||
+ | | 4 |SAB - Software abort \\ %1: Stop channel| | ||
+ | | 3 |INT - Interrupt enable \\ %0: Enable interrupt \\ %1: Disable interrupt| | ||
+ | | 2~0 |0| | ||
+ | |||
+ | --- | ||
+ | |||
+ | MTC< | ||
+ | Number of transfer operands. | ||
+ | |||
+ | --- | ||
+ | |||
+ | MAR< | ||
+ | Start memory transfer address. | ||
+ | |||
+ | --- | ||
+ | |||
+ | DAR< | ||
+ | Start device transfer adddress. | ||
+ | |||
+ | --- | ||
+ | |||
+ | BTC< | ||
+ | Number of transfer blocks (the number of transfer information tables) in array chain mode. | ||
+ | |||
+ | --- | ||
+ | |||
+ | BAR< | ||
+ | Start address of the transfer information table in array chain/link array chain mode. | ||
+ | |||
+ | --- | ||
+ | |||
+ | NIC< | ||
+ | Vector number to be used for interrupt generated when CSR ERR is %0. | ||
+ | |||
+ | --- | ||
+ | |||
+ | EIV< | ||
+ | Vector number to be used for the interrupt generated when CSR ERR is %1. | ||
+ | |||
+ | --- | ||
+ | |||
+ | MFC< | ||
+ | |||
+ | ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | ||
+ | | 0 ||||| FC2 | FC1 | FC0 | | ||
+ | |||
+ | ^Bits^Description^ | ||
+ | | 7~3 |0| | ||
+ | | 2~0 |Memory function code \\ %000: Unused \\ %001: User data \\ %010: User program \\ %011: Unused \\ %100: Unused \\ %101: Supervisor data \\ %110: Supervisor program \\ %111: Interrupt acknowledge| | ||
+ | |||
+ | --- | ||
+ | |||
+ | CPR< | ||
+ | |||
+ | ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | ||
+ | | 0 |||||| | ||
+ | |||
+ | ^Bits^Description^ | ||
+ | | 7~2 |0| | ||
+ | | 1~0 |CP - Channel priority \\ %00: Highest priority \\ %01: Second highest priority \\ %10: Third highest priority \\ %11: Lowest priority| | ||
+ | |||
+ | --- | ||
+ | |||
+ | DFC< | ||
+ | Same as MFC. | ||
+ | |||
+ | --- | ||
+ | |||
+ | BFC< | ||
+ | Same as MFC. | ||
+ | |||
+ | --- | ||
+ | |||
+ | GCR< | ||
+ | |||
+ | ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | ||
+ | | 0 |||| BT || BR || | ||
+ | |||
+ | ^Bits^Description^ | ||
+ | | 7~4 |0| | ||
+ | | 3~2 |BT - Burst time \\ Number of DMA clock cycles per burst. \\ %00: 16 clocks \\ %01: 32 clocks \\ %10: 64 clocks \\ %11: 129 clocks| | ||
+ | | 1~0 |BR - Bandwidth threshold (band occupancy) \\ %00: 50% \\ %01: 25% \\ %10: 12.5% \\ %11: 6.25% \\ Note: Only affects channels set to limited speed auto request mode| |
x68000/dmac.txt · Last modified: 2019/08/27 20:45 by 127.0.0.1