schematics:megadrivechips
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+ | ==== Genesis/ | ||
+ | ==== Genesis/ | ||
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+ | The original Genesis/ | ||
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+ | === VDP === | ||
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+ | Arguably the most important was the VDP, which contained all of the display logic necessary to generate the images. This chip generated the clock signals for the 68000/ | ||
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+ | === Bus Arbiter === | ||
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+ | The Bus Arbiter existed solely to ensure that access between the Z80, the 68000 and the VDP was shared fairly and did not clash. It connects to both the Z80 and the 68000 address busses, and generates a bunch of the control signals necessary for these chips (and the memory) to operate correctly. This chip is in position IC-4. | ||
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+ | === I/O === | ||
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+ | The I/O chip was responsible for handling external I/O such as the joystick and modem (EXT) ports, as well as providing the means for the 68000 and Z80 to communicate with each other. It also creates the EDCK line, also known as HS_CLK in some pinouts. The I/O chip can be found in position IC-5. | ||
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+ | ==== Other Genesis/ | ||
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+ | Unfortunately, | ||
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+ | Later revisions of the Genesis/ | ||
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+ | Images seen suggest that there may have been a version where the VDP, Bus Arbiter and the I/O chip were merged into a single ASIC. |
schematics/megadrivechips.txt · Last modified: 2019/08/27 20:45 by 127.0.0.1