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schematics:megadrivechips [2005/11/10 03:19] – created aidanschematics:megadrivechips [2019/08/27 20:45] (current) – external edit 127.0.0.1
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 Arguably the most important was the VDP, which contained all of the display logic necessary to generate the images. This chip generated the clock signals for the 68000/YM-2612 and the Z80. It had 64K of local V-RAM (Video memory), in the form of IC9 and IC10 (uPD41264V-12). This allowed it to perform operations independantly from the rest of the system, thus avoiding issues with bus arbitration when it came to display memory. It also contained the three DAC for producing an RGB signal as well as the necessary sync. As if that were not enough, it also contained a programmable sound generator (PSG) for basic sound effects. This would be mixed in with the YM-2612 soundchip elsewhere. On an original Genesis/Megadrive, this was marked as IC-8. Arguably the most important was the VDP, which contained all of the display logic necessary to generate the images. This chip generated the clock signals for the 68000/YM-2612 and the Z80. It had 64K of local V-RAM (Video memory), in the form of IC9 and IC10 (uPD41264V-12). This allowed it to perform operations independantly from the rest of the system, thus avoiding issues with bus arbitration when it came to display memory. It also contained the three DAC for producing an RGB signal as well as the necessary sync. As if that were not enough, it also contained a programmable sound generator (PSG) for basic sound effects. This would be mixed in with the YM-2612 soundchip elsewhere. On an original Genesis/Megadrive, this was marked as IC-8.
  
- *  [[vdppinout|VDP Pinout]]+ *  [[megadrive1vdppinout|VDP Pinout]]
  
 === Bus Arbiter === === Bus Arbiter ===
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 The Bus Arbiter existed solely to ensure that access between the Z80, the 68000 and the VDP was shared fairly and did not clash. It connects to both the Z80 and the 68000 address busses, and generates a bunch of the control signals necessary for these chips (and the memory) to operate correctly. This chip is in position IC-4. The Bus Arbiter existed solely to ensure that access between the Z80, the 68000 and the VDP was shared fairly and did not clash. It connects to both the Z80 and the 68000 address busses, and generates a bunch of the control signals necessary for these chips (and the memory) to operate correctly. This chip is in position IC-4.
  
- *  [[bapinout|Bus Arbiter Pinout]]+ *  [[megadrive1bapinout|Bus Arbiter Pinout]]
  
 === I/O === === I/O ===
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 The I/O chip was responsible for handling external I/O such as the joystick and modem (EXT) ports, as well as providing the means for the 68000 and Z80 to communicate with each other. It also creates the EDCK line, also known as HS_CLK in some pinouts. The I/O chip can be found in position IC-5. The I/O chip was responsible for handling external I/O such as the joystick and modem (EXT) ports, as well as providing the means for the 68000 and Z80 to communicate with each other. It also creates the EDCK line, also known as HS_CLK in some pinouts. The I/O chip can be found in position IC-5.
  
- *  [[iopinout|I/O Pinout]]+ *  [[megadrive1iopinout|I/O Pinout]]
  
 ==== Other Genesis/Megadrive versions ==== ==== Other Genesis/Megadrive versions ====
  
-Unfortunately, no information is currently present for other varients. If you have any, please add this information!+Unfortunately, little information is currently present for other variants. If you have any, please add this information! 
 + 
 +Later revisions of the Genesis/Megadrive merged the three chip setup into two chips. This makes sense from a cost point of view, but we do not currently have any pinout information for these chips. 
 + 
 +Images seen suggest that there may have been a version where the VDP, Bus Arbiter and the I/O chip were merged into a single ASIC.
schematics/megadrivechips.1131556787.txt.gz · Last modified: 2019/08/27 20:44 (external edit)