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schematics:msxexpansion [2009/07/08 16:12]
174.6.65.172 created
schematics:msxexpansion [2019/08/27 20:45] (current)
Line 3: Line 3:
  
 Female 50 pin connector Female 50 pin connector
 +
 +{{:​schematics:​msxcartpinout.jpg|}}
 +
  
    ​1:/​CS1 ​         2:/CS2    ​1:/​CS1 ​         2:/CS2
Line 30: Line 33:
   49: SOUNDIN ​    50: -12V            ​   49: SOUNDIN ​    50: -12V            ​
                                                                                
-{{:​schematics:​msxcartpinout.jpg|}} 
  
  
Line 37: Line 39:
  
  
- ​1 ​   ROM addresses 4000-7FFF select signal + 1-ROM addresses 4000-7FFF select signal 
- ​2 ​   ROM addresses 8000-BFFF select signal +  
- ​3 ​   ROM addresses 4000-BFFF select signal (for 256k ROM) +  
- ​4 ​   Slot select signal + 
- ​5 ​   Reserved signal line - use inhibited + 2-ROM addresses 8000-BFFF select signal 
- ​6 ​   Refresh cycle signal +  
- ​7 ​   CPU's WAIT request signal + 
- ​8 ​   Interrupt request signal to CPU + 3-ROM addresses 4000-BFFF select signal (for 256k ROM) 
- ​9 ​   Signal expressing CPU fetch cycle + 
-10    This signal controls direction of external databus buffer + 4-Slot select signal 
-      Cartridges are selected and L level is output from each + 
-      cartridge at data transmission time + 5-Reserved signal line - use inhibited 
-11    I/O request signal + 
-12    Memory request signal + 6-Refresh cycle signal 
-13    Write timing signal + 
-14    Read timing signal + 7-CPU's WAIT request signal 
-15    System reset signal + 
-16    Reserved signal line - use inhibited + 8-Interrupt request signal to CPU 
-17-32 Address bus signals + 
-33-40 Data bus signals + 9-Signal expressing CPU fetch cycle 
-41    Signal ground + 
-42    CPU clock 3.579545MHz +10-This signal controls direction of external databus buffer 
-43    Signal ground +Cartridges are selected and L level is output from each  
-44,46 For insertion/​removal protect +cartridge at data transmission time 
-45,47 +5V power source + 
-48    +12V power source +11-I/O request signal 
-49    Sound input signal (-5bdm) + 
-50    -12V power source+12-Memory request signal 
 + 
 +13-Write timing signal 
 + 
 +14-Read timing signal 
 + 
 +15-System reset signal 
 + 
 +16-Reserved signal line - use inhibited 
 + 
 +17-32-Address bus signals 
 + 
 +33-40-Data bus signals 
 + 
 +41-Signal ground 
 + 
 +42-CPU clock 3.579545MHz 
 + 
 +43-Signal ground 
 + 
 +44,46-For insertion/​removal protect 
 + 
 +45,47+5V power source 
 + 
 +48+12V power source 
 + 
 +49-Sound input signal (-5bdm) 
 + 
 +50-12V power source
  
 
 schematics/msxexpansion.txt · Last modified: 2019/08/27 20:45 (external edit)
 
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