Differences

This shows you the differences between two versions of the page.

--- x68000:dmac [2017/09/11 10:31] – add some newlines neko68k
+++ x68000:dmac [2017/09/11 10:53] – forgot register names for the last 4 neko68k
@@ Line 36: / Line 36: @@
 |+0x27|1.b|R/W|[[dmac#eiv|EIV]] - Error Interrupt Vector|
 |+0x28|1.b| |---|
-|+0x29|1.b|R/W|MFC - Memory Function Code|
+|+0x29|1.b|R/W|[[dmac#mfc|MFC]] - Memory Function Code|
 |+0x2A|1.w| |---|
 |+0x2C|1.b| |---|
-|+0x2D|1.b|R/W|CPR - Channel Priority Register|
+|+0x2D|1.b|R/W|[[dmac#cpr|CPR]] - Channel Priority Register|
 |+0x2E|1.w| |---|
 |+0x30|1.b| |---|
-|+0x31|1.b|R/W|DFC - Device Function Code|
+|+0x31|1.b|R/W|[[dmac#dfc|DFC]] - Device Function Code|
 |+0x32|3.w| |---|
 |+0x38|1.b| |---|
-|+0x39|1.b|R/W|BFC - Base Function Code|
+|+0x39|1.b|R/W|[[dmac#bfc|BFC]] - Base Function Code|
 |+0x3A|1.l| |---|
 |+0x3E|1.b| |---|
-|+0x3F|1.b|R/W|GCR - General Control Register|
+|+0x3F|1.b|R/W|[[dmac#gcr|GCR]] - General Control Register|
 ===== Register Descriptions =====
@@ Line 178: / Line 178: @@
 EIV<BOOKMARK:eiv> - Error Interrupt Vector (+0x27) \\
 Vector number to be used for the interrupt generated when CSR ERR is %1.
+---
+MFC<BOOKMARK:mfc> - Memory Function Code (+0x29)
+^  7  ^  6  ^  5  ^  4  ^  3  ^  2  ^  1  ^  0  ^
+|  0  |||||  FC2  |  FC1  |  FC0  |
+^Bits^Description^
+|  7~3  |0|
+|  2~0  |Memory function code \\ %000: Unused \\ %001: User data \\ %010: User program \\ %011: Unused \\ %100: Unused \\ %101: Supervisor data \\ %110: Supervisor program \\ %111: Interrupt acknowledge|
+---
+CPR<BOOKMARK:cpr> - Channel Priority Register (+0x2D)
+^  7  ^  6  ^  5  ^  4  ^  3  ^  2  ^  1  ^  0  ^
+|  0  ||||||  CP  ||
+^Bits^Description^
+|  7~2  |0|
+|  1~0  |CP - Channel priority \\ %00: Highest priority \\ %01: Second highest priority \\ %10: Third highest priority \\ %11: Lowest priority|
+---
+DFC<BOOKMARK:DFC> - Device Function Code (+0x31)
+Same as MFC.
+---
+BFC<BOOKMARK:BFC> - Base Function Code (+0x39)
+Same as MFC.
+---
+GCR<BOOKMARK:GCR> - General Control Register (+0x3F)
+^  7  ^  6  ^  5  ^  4  ^  3  ^  2  ^  1  ^  0  ^
+|  0  ||||  BT  ||  BR  ||
+^Bits^Description^
+|  7~4  |0|
+|  3~2  |BT - Burst time \\ Number of DMA clock cycles per burst. \\ %00: 16 clocks \\ %01: 32 clocks \\ %10: 64 clocks \\ %11: 129 clocks|
+|  1~0  |BR - Bandwidth threshold (band occupancy) \\ %00: 50% \\ %01: 25% \\ %10: 12.5%  \\ %11: 6.25% \\ Note: Only affects channels set to limited speed auto request mode|