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Table of Contents
DMAC
The HD63450 has four DMA channels. On the X68000 channels #0, #1 and, #3 are assigned respectively to FD, HD, and ADPCM. Channel #2 REQ(DMA transfer request signal), ACK(response signal), and PCL (general purpose input signal) is available to the user. It can be used for transfers between memory and memory and between memory and expansion boards.
The registers for the DMAC exist starting at 0xE84000 and there are 0x40 bytes for each channel. GCR (General Control Register) is only available on channel #3.
Addresses
| Address | Channel |
|---|---|
| 0xE84000 | #0 |
| 0xE84040 | #1 |
| 0xE84080 | #2 |
| 0xE840C0 | #3 |
Register List
| Offset | Size | R/W | Description |
|---|---|---|---|
| +0x00 | 1.b | R/W | CSR - Channel Status Register |
| +0x01 | 1.b | R | CER - Channel Error Register |
| +0x02 | 1.w | — | |
| +0x04 | 1.b | R/W | DCR - Device Control Register |
| +0x05 | 1.b | R/W | OCR - Operation Control Register |
| +0x06 | 1.b | R/W | SCR - Sequence Control Register |
| +0x07 | 1.b | R/W | CCR - Channel Control Register |
| +0x08 | 1.w | — | |
| +0x0A | 1.w | R/W | MTC - Memory Transfer Control |
| +0x0C | 1.l | R/W | MAR - Memory Address Register |
| +0x10 | 1.l | — | |
| +0x14 | 1.l | R/W | DAR - Device Address Register |
| +0x18 | 1.w | — | |
| +0x1A | 1.w | R/W | BTC - Base Transfer Counter |
| +0x1C | 1.l | R/W | BAR - Base Address Register |
| +0x20 | 1.l | — | |
| +0x24 | 1.b | — | |
| +0x25 | 1.b | R/W | NIV - Normal Interrupt Vector |
| +0x26 | 1.b | — | |
| +0x27 | 1.b | R/W | EIV - Error Interrupt Vector |
| +0x28 | 1.b | — | |
| +0x29 | 1.b | R/W | MFC - Memory Function Code |
| +0x2A | 1.w | — | |
| +0x2C | 1.b | — | |
| +0x2D | 1.b | R/W | CPR - Channel Priority Register |
| +0x2E | 1.w | — | |
| +0x30 | 1.b | — | |
| +0x31 | 1.b | R/W | DFC - Device Function Code |
| +0x32 | 3.w | — | |
| +0x38 | 1.b | — | |
| +0x39 | 1.b | R/W | BFC - Base Function Code |
| +0x3A | 1.l | — | |
| +0x3E | 1.b | — | |
| +0x3F | 1.b | R/W | GCR - General Control Register |
Register Descriptions
CSR<BOOKMARK:csr> - Channel Status Register
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| COC | BTC | NDT | ERR | ACT | DIT | PCT | PCS |
| Bits | Name | Description |
|---|---|---|
| 7 | COC | Channel Operation Complete %0: Channel operation incomplete %1: Channel operation complete |
| 6 | BTC | Block Transfer Complete %0: Block transfer incomplete %1: Block transfer complete |
| 5 | NDT | Normal Device Termination %0: Not stopped due to DONE signal %1: Stopped due to DONE signal |
| 4 | ERR | Error bit %0: No error %1: Error occurred (ERROR CODE bit contains error) |
| 3 | ACT | Channel Active %0: Channel inactive %1: Channel active |
| 2 | DIT | DONE Input Transition %0: No DONE input %1: There was a DONE input when the BTD bit of OCR was %1 |
| 1 | PCT | PCL Transition %0 There is no PCL transition (High→Low transition) %1: PCL transition occured |
| 0 | PCS | PCL Status Line %0: PCL = Low %1: PCL = high |
Note: When a bit other than ACT or PCS becomes %1 it remains %1 until %1 is written to that bit or a reset is applied. In particular it is necessary to clear COC, BTC, NDT, ERR, and ACT since it is not possible to perform the next transfer operation while they are %1.
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