x68000:crtc_registers
Overview
Horizontal timing control
Address | Size | R/W | Name | Description |
---|---|---|---|---|
$E80000 | 1.w | W | R00 | Horizontal total |
$E80002 | 1.w | W | R01 | HSYNC end position |
$E80004 | 1.w | W | R02 | HDISP start position |
$E80006 | 1.w | W | R03 | HDISP end position |
Vertical timing control
Address | Size | R/W | Name | Description |
---|---|---|---|---|
$E80008 | 1.w | W | R04 | Vertical total |
$E8000A | 1.w | W | R05 | VSYNC end position |
$E8000C | 1.w | W | R06 | VDISP start position |
$E8000E | 1.w | W | R07 | VDISP end position |
Misc 1
Address | Size | R/W | Name | Description |
---|---|---|---|---|
$E80010 | 1.w | W | R08 | External sync horiz adjustment : Horiz position fine adjust |
$E80012 | 1.w | W | R09 | Raster number : For raster interrupt |
Text layer scroll
Address | Size | R/W | Name | Description |
---|---|---|---|---|
$E80014 | 1.w | W | R10 | X scroll |
$E80016 | 1.w | W | R11 | Y scroll |
Graphic layer scroll
Address | Size | R/W | Name | Description |
---|---|---|---|---|
$E80018 | 1.w | W | R12 | X0 |
$E8001A | 1.w | W | R13 | Y0 |
$E8001C | 1.w | W | R14 | X1 |
$E8001E | 1.w | W | R15 | Y1 |
$E80020 | 1.w | W | R16 | X2 |
$E80022 | 1.w | W | R17 | Y2 |
$E80024 | 1.w | W | R18 | X3 |
$E80026 | 1.w | W | R19 | Y3 |
Misc 2
Address | Size | R/W | Name | Description |
---|---|---|---|---|
$E80028 | 1.w | R/W | R20 | Memory mode/display mode control |
$E8002A | 1.w | R/W | R21 | TVRAM simultaneous access/raster copy/fast clear plane selection |
$E8002C | 1.w | W | R22 | For raster copy operation: raster number |
$E8002E | 1.w | W | R23 | TVRAM access mask pattern |
$E80481 | 1.b | R/W | Image capture/fast clear/raster copy control |
Details
CRTC R00($e80000):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │ │HTOTAL | └───────────────┴───────────────┘ HSYNC period × horiz width R00 = ────────────────────────── -1 Display period × 8 ※LSB must be 1
CRTC R01($e80002):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │ │HSYNC end | └───────────────┴───────────────┘ HSYNC pulse width × horiz width R01 = ───────────────────────────────── -1 Display period × 8
CRTC R02($e80004):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │ │HDISP start | └───────────────┴───────────────┘ (HSYNC pulse width + horiz back porch) × horiz width R02 = ───────────────────────────────────────────────────── -5 Display period × 8
CRTC R03($e80006):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │ │HDISP end | └───────────────┴───────────────┘ (HSYNC pulse width - horiz front porch) × horiz width R03 = ────────────────────────────────────────────────────── -5 Display period × 8
CRTC R04($e80008):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │ │VTOTAL | └───────────────┴───────────────┘ VSYNC period R04 = ──────────── -1 HSYNC period
CRTC R05($e8000a):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │ │VSYNC end | └───────────────┴───────────────┘ VSYNC pulse width R05 = ───────────────── -1 HSYNC period
CRTC R06($e8000c):
bit 15 10 9 0 ┌───────────┬───────────────────┐ │ │ VDISP start │ └───────────┴───────────────────┘ VSYNC pulse width + Vertical back porch R06 = ──────────────────────────────────────── -1 HSYNC period
CRTC R07($e8000e):
bit 15 10 9 0 ┌───────────┬───────────────────┐ │ │ VDISP end │ └───────────┴───────────────────┘ VSYNC pulse width - vertical front porch R07 = ───────────────────────────────────────── -1 HSYNC period
CRTC R08($e80010):
bit 15 8 7 0 ┌───────────────┬───────────────────────┐ │ │ EXT sync horiz adjust │ └───────────────┴───────────────────────┘
CRTC R09($e80012):
bit 15 10 9 0 ┌───────────┬───────────────────┐ │ │ Raster number │ └───────────┴───────────────────┘ VSYNC pulse width + vertical back porch R09 = ────────────────────────────────────────── + raster number HSYNC period = R06 +1 + raster number
CRTC R10($e80014):
bit 15 10 9 0 ┌───────────┬───────────────────┐ │ │ X Scroll │ └───────────┴───────────────────┘
CRTC R11($e80016):
bit 15 10 9 0 ┌───────────┬───────────────────┐ │ │ Y Scroll │ └───────────┴───────────────────┘
CRTC R12($e80018):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ X0 │ └───────────┴───────────────────┘ ※In 512x512 mode bits 0~8 are effective.
CRTC R13($e8001a):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ Y0 │ └───────────┴───────────────────┘ ※In 512x512 mode bits 0~8 are effective.
CRTC R14($e8001c):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ X1 │ └───────────┴───────────────────┘ ※Unused in 1024x1024 mode.
CRTC R15($e8001e):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ Y1 │ └───────────┴───────────────────┘ ※Unused in 1024x1024 mode.
CRTC R16($e80020):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ X2 │ └───────────┴───────────────────┘ ※Unused in 1024x1024 mode.
CRTC R17($e80022):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ Y2 │ └───────────┴───────────────────┘ ※Unused in 1024x1024 mode.
CRTC R18($e80024):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ X3 │ └───────────┴───────────────────┘ ※Unused in 1024x1024 mode.
CRTC R19($e80026):
bit 15 10 9 8 0 ┌───────────┬───────────────────┐ │ │ │ Y3 │ └───────────┴───────────────────┘ ※Unused in 1024x1024 mode.
CRTC R20($e80028):
bit 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ┌───────┬──┬──┬──┬────────┬─────┬──┬───┬───┐ │ │ │ │ │ COL │ │HF│VD │HD │ └───────┴──┴──┴──┴────────┴─────┴──┴───┴───┘ │ │ └ SIZE │ G-MEM └ T-MEM
bit 12 T-MEM T-VRAM Usage mode %0 : Display %1 : Buffer bit 11 G-MEM G-VRAM Usage mode %0 : Display %1 : Buffer(bit 10~8 are invalid) (G-VRAM in buffer mode has the same structure as 65535 color mode) bit 10 SIZE GVRAM size %0 : 512× 512 pixel %1 : 1024×1024 pixel bit 9~8 COL GVRAM Color mode %00 : 16 colors %01 : 256 colors %10 : Undefined %11 : 65536 colors bit 4 HF Horizontal deflection frequency %0 : 15.98kHz %1 : 31.50kHz bit 3~2 VD Vertical size %00 : 256 pixels %01 : 512 pixels %10 : 1024 pixels - Interlace (Only when HF = %1) %11 : 〃 bit 1~0 HD Horizontal size %00 : 256 pixels %01 : 512 pixels %10 : 768 pixels %11 : 50MHz CRTC clock (Compact XVI and later only without modification)
CRTC R21($e8002a):
bit 15 10 9 8 7 6 5 4 3 2 1 0 ┌───────────┬─┬─┬───────┬───────┐ │ │ │ │ │ │ │ │ │ │ │ │ └───────────┴─┴─┴───────┴───────┘ │ │AP3~AP0 CP3~CP0 MEN SA
bit 9 MEN Text screen access mask %0 : Disabled %1 : Enabled bit 8 SA Text screen simultaneous access %0 : Disabled %1 : Enabled bit 7~4 AP3~AP0 Text screen simultaneous access plane selection %0 : Selected %1 : Unselected bit 3~0 CP3~CP0 ┌ Text layer raster copy target plane └ G-VRAM high speed clear target page %0 : Selected %1 : Unselected
CRTC R22($e8002c):
bit 15 8 7 0 ┌───────────────┬───────────────┐ │Source raster │Dest raster │ └───────────────┴───────────────┘ (Transfer source) (Transfer dest)
CRTC R23($e8002e):
bit 15 0 ┌────────────────────────────────────┐ │Text layer simultaneous mask pattern│ └────────────────────────────────────┘ %0 : Data is written %1 : Data is not written
CRTC Control port($e80481):
bit 7 4 3 2 1 0 ┌───────┬──┬─┬──┬──┐ │ │RC│0│FC│VI│ └───────┴──┴─┴──┴──┘
bit 3 RC Text layer raster copy start %0 : Stop %1 : Start bit 1 FC Graphic layer fast clear start %0 : Stop %1 : Start ※Automatically becomes 0 after operation completes bit 0 VI Image capture start %0 : Stop %1 : Start
x68000/crtc_registers.txt · Last modified: 2019/08/27 20:45 by 127.0.0.1